1. Field of the Invention
The present invention provides a method for avoiding deterioration of a dielectric characteristic of a dielectric layer having a low dielectric constant (low k), during a stripping process.
2. Description of the Prior Art
With the decreasing size of semiconductor devices and an increase in integrated circuits (IC) density, RC time delay, produced between the metal wires, seriously affects IC operation performance and reduces IC operating speed. RC time delay effects are more obvious especially when the line width is reduced to 0.25 μm, even 0.13 μm in semiconductor process.
RC time delay produced between metal wires is a product of the electrical resistance (R) of the metal wires and the parasitic capacitance (C) of a dielectric layer between the metal wires. However, there are two approaches to reduce RC time delay: a) using conductive materials with a lower resistance as a metal wire or, b) reducing the parasitic capacitance of the dielectric layer between metal wires. In the approach of using a metal wire with a lower resistance, copper interconnection technology replaces the traditional Al:Cu(0.5%) alloy fabrication process and is a necessary tendency in multilevel metallization processes. Due to copper having a low resistance (1.67 μΩ-cm) and higher current density load without electro-migration in the Al/Cu alloy, the parasitic capacitance between metal wires and connection levels of metal wires is reduced. However, reducing RC time delay produced between metal wires by only copper interconnection technology is not enough. Also, some fabrication problems of copper interconnection technology need to be solved. Therefore, it is more and more important to reduce RC time delay by the approach of reducing the parasitic capacitance of the dielectric layer between metal wires.
Additionally, the parasitic capacitance of a dielectric layer is related to the dielectric constant of the dielectric layer. As the dielectric constant of the dielectric layer is lower, the parasitic capacitance of the dielectric layer is lower. Traditionally silicon dioxide (dielectric constant is 3.9) cannot meet the requirement of 0.13 μm in semiconductor processes, so some new low k materials, such as polyimide (PI), FPI, FLARE™, PAE-2, PAE-3 or LOSP are thereby consecutively proposed.
Unfortunately, the these low k materials are composed of carbon, hydrogen and oxygen and have significantly different properties to those of traditional silicon dioxide used in etching or adhering with other materials. Most of these low k materials have some disadvantages such as poor adhesion and poor thermal stability, so they cannot properly integrate into current IC fabrication processes.
Therefore, another kind of low k dielectric layer, such as HSQ (hydrogen silsesquioxane) (k=2.8), MSQ (methyl silsesquioxane)(k=2.7), HOSP (k=2.5), H-PSSQ (hydrio polysilsesquioxane), M-PSSQ (methyl polysilsesquioxane), P-PSSQ (phenyl polysilsesquioxane) and porous sol-gel, using the silicon dioxide as a base and adding some carbon and hydrogen elements inside is needed. These silicon based low k materials have potential in the future since properties of these materials resemble traditional silicon dioxide and can be easily integrated into the current IC fabrication process.
However, when patterning a dielectric layer composed of silicon dioxide based low k materials, the dielectric layer suffers some damages during an etching or stripping process. Since the stripping process usually uses dry oxygen plasma ashing and wet stripper to remove a photoresist layer, the bonds in a surface of the dielectric layer are easily broken by oxygen plasma bombardment and react with oxygen radical and wet stripper to form Si—OH bonds. Since the Si—OH bonds absorb water moisture and the water dielectric constant is very high (k=78), the dielectric constant and leakage current of the dielectric layer are increased, and even a phenomenon of poison via occurs, thereby seriously affecting the reliability of products.